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Analog IC Deisgn Engineer

Minimum of five years of analog IC/IP design eperience, MSEE or Ph.D. EE degree preferred. Candidates will join the R&D team and design the state-of-the-art high performance analog IC circuits, including PLL, ADC, DAC and Power Management. The candidate should be familiar with analog IC design tools such as Cadence, Synopsys and Mentor tools.

Analog IC Layout Engineer

Minimum of three years of layout experience, BSEE degree preferred. Candidate will layout high speed, high performance analog circuits for analog and mixed-signal IP cores, including PLL, ADC, DAC and Power Management. The candidate should have experience in Cadence composer, Virtuoso tools, Mentor Caliber tools for LVS, DRC and RC extraction.  65nm / 55nm / 40nm experiences a plus.

ASIC Design Engineer

Responsible for the design, verification and evaluation of digital circuits. Duties include product specification, RTL coding, verification, synthesis, timing analysis, SOC integration, test pattern development and bench characterization.  Requires in depth understanding of DSP systems and algorithms, FIR/IIR filters, adaptive filters.  Familiar with Matlab, C and assembly languages.  MSEE or Ph.D. EE with 3+ years of experience.

Please contact:

Human Resources Department
Attn: Susan
Berkeley Analog, Inc.
898 Faulstict Ct
San Jose, CA 95112

HR@BerkeleyAnalog.com

Berkeley Analog, Inc. is an equal opportunity employer.